1. Field of the Invention
The present invention relates to a semiconductor memory device for a highly-integrated Dynamic Random Access Memory (DRAM) or the like which operates at high speed, and, in particular, to a low-cost semiconductor memory device which can be operated in a block write mode, wherein the number of spare columns is less than the number of columns which are a block unit when in the block write mode, and wherein an increase in the chip area of the semiconductor memory device can be decreased.
2. Description of the Prior Art
Because a DRAM used as a random access port section for an image memory is used as a frame buffer in which display data to be displayed is saved, a function for rapidly rewriting data is required. One function which satisfies this requirement is a block write mode.
The block write mode can be defined as a mode for writing data items into a plurality of columns simultaneously, in the case where lowest N bits (where N is an integer, 1 or greater) of a column address for the DRAM entered from an external section are irrelevant.
It is also possible for each column to be selectively masked (not written into) in the block write mode.
FIG. 1 is a diagram for roughly explaining a memory cell section including spare columns, and for explaining the relationship between data lines which connect the memory cell section with peripheral sections, column decoders, column decoder lines, and column addresses, in a DRAM which includes functions such as the block write mode described above.
In FIG. 1, the data lines DQ0 to DQ3 are normally complementary lines, and each of the data lines DQ0 to DQ3 is formed as a pair of unit lines. However, to avoid complications, each pair of data lines is shown as one line in FIG. 1. Also, for simplicity, the number of I/Os of data is one and the number of columns is 16 columns in the following explanation. In addition, the number of columns in the block write mode is four columns in order to write four data items into the memory cells at the same time, where the required column addresses are A0C to A3C and inverted phase signal of the column addresses are /A0C to /A3C.
The reference numeral 100 designates a DQ buffer connecting the memory cell section and the peripheral section. The DQ buffer 100 decodes and amplifies data from a memory cell in the memory cell section and transmits this data to an output buffer 300 in the peripheral section via a read-out data line 30. The DQ buffer 100 can also decode and amplify data from an input buffer 200 in the peripheral section and write this data into a memory cell. The written-in data is provided to the DQ buffer 100 from the input buffer 200 via a write-in data line 20. The DQ buffer 100 drives the data line pairs DQ0 to DQ3.
However, four pairs of data lines are required during block write mode because four columns must be masked independently. In the case where four columns are all written into without being masked, the four pairs of data line pairs DQ0 to DQ3 are all driven. The data line pairs corresponding to these columns are not driven under the control of the DQ buffer 100 when there is a column to be masked.
FIGS. 2A, 2B and FIGS. 3A, 3B are circuit diagrams for column decoders NCDO, NCD1, . . . , NCD3 and a spare column decoder SCD.
In the case of a later-described read/write mode for one bit, the column decoder system has the following configuration in order to reduce current consumption in idle data line pairs. Specifically, two columns are selected through each of column selection lines CSL0 to CSL7 and spare column selection lines SCSL0 and SCSL1 two columns.
The last two bits A1C and A0C in a column address signal are converted to partial column decoding address signal Y0 to Y3 by a partial column decoder CPD shown in FIGS. 4A and 4B and transmitted to the DQ buffer 100, then one pair is selected from the four decoder line pairs 50. The last second to last bit A1C in a column address signal together with a block write mode signal BW, which changes to a high potential level during only the block write mode.
The operation of the conventional semiconductor memory device as a conventional example will now be explained.
When the block write mode is selected, the block write mode signal BW is changed to the high potential from a low potential. As can be understood from FIGS. 2A and 2B, there is no relation to the column address signals A1C and /A1C because a column decoder control signal CSP, which is transmitted into a three input NAND gate in the column decoder NCDm to be selected (where m=0, 1, . . . , 3), is at the high potential level, therefore in spite of values of the voltage potentials of the column address A1C and /A1C, both a column selection line CSL2m and a column selection line CSL2m+1 (where m=0 to 3) are selected together.
In addition, as can be understood from FIGS. 4A and 4B, during the block write mode, the data from the write-in data line 20 is transmitted to four data line pairs 50 without being decoded in the DQ buffer 100, irrespective of the lowest two bits A1C and /A1C in the column address signals, because the partial column decoder address signals Y0 to Y3 supplied to the DQ buffer 100 are all at the high potential. At this time, the column selection line CSL2m and the column selection line CSL2m+1 are selected together so that the write-in data is finally written into the four columns. In this case, four of the data line pairs DQ0 to DQ3 are charged and discharged together.
Next, the operation of the conventional semiconductor memory device during a normal one-bit read/write mode will be outlined. In the case of the one-bit read/write mode, the column address having all bits (A0C to A3C and /A0C to /A3C) are transmitted. Also, the block write mode signal BW is at the low potential.
The reason is that either the column selection line CSL2m or the column selection line CSL2m+1 is selected in accordance with the potential of the column address signals A1C and /A1C, as can be understood from FIGS. 2A and 2B. Also, as can be understood from FIGS. 4A and 4B, because the block write mode signal BW is at the low potential in accordance with the potential of the two lowest bits A1C and A0C in the column address signal, only one of the partial column decoder addresses Y0 to Y3 supplied to the DQ buffer 100 is at the high potential, therefore the specified decoding operation is performed by the DQ buffer 100.
For example, in the case of the read mode, when one of the column selection lines CSL is selected, data items of two columns are read from two groups of data line pairs. Then, the decoding of the remaining column addresses is implemented by the DQ buffer 100, and finally only data of one column is read out to the data line 30. In addition, nothing is done to the remaining two columns belonging to the column selection lines CSL which are not selected.
Also, in the write mode, data from the write-in data line 20 is supplied to the DQ buffer 100, then the two lowest bits A1C and A0C of the column address signal are decoded, and write-in data is transmitted to only one of the data line pairs. This data is written into the memory cell corresponding to the provided address via the selected column selection line CSL.
Finally, data in the memory cell corresponding to the same column selection line CSL and the one remaining unselected column is read out to a data line pair.
In addition, nothing is done with the remaining two columns belonging to the unselected column selection lines CSL.
Accordingly, the current consumption of the data line pairs is reduced by half in comparison with the case in block write mode, because there are only two data line pairs in both the read and write operations.
In this manner, the charging and discharging of unnecessary data line pairs are avoided, with the result that an increase in the current consumption can be decreased by changing the number of column selection lines CSL selected in the block write mode and other modes.
In the foregoing explanation, n, the number of I/Os, is assumed to be 1 in order to simplify the explanation, but in practice, n is not limited to 1. Also, in the above explanation the number of columns is taken as 16, and an example is given wherein the number of columns per one column selection line CSL in a four column block write mode is two columns. However, in principle, any number of columns and any number of block write columns may be used.
As outlined above, this conventional example is basically a circuit configuration corresponding to the block write mode, and, depending on the mode such as the read/write mode, is an example of a circuit configuration by which it is possible to reduce current consumption.
However, problems are produced in accordance with the increase in the number of columns for block write mode and the number of I/Os. These problems will now be described. Normally, in a semiconductor memory device, defects develop which are attributable to the memory cells, word lines and bit lines, or the like. As a result of these defects, redundant cells (spare rows, spare columns) are provided to counter a drop in yields. For example, if defects are produced in a certain column, the address of this defective column is programmed in advance in a comparator, and in the case where a column address provided from an external device and the programmed address are in agreement, a number of columns including this defective column are replaced by spare columns and then accessed.
There are no particular criteria as to which columns are provided as spare columns. There are cases where this number is determined as a function of the memory. For example, FIG. 1 is a general configuration drawing showing spare columns and a spare column selection line system for a conventional DRAM in which a four-column (N=2) block write function is provided. In this case, four columns (SCOL0 TO SCOL3) are required as spare columns to access four columns together during block write mode.
Below, an explanation will be given for an example of operation in the case where a defective column is present in the conventional semiconductor memory device, with reference to FIGS. 2A, 2B and FIGS. 3A, 3B. For simplification, a column COL0 is taken as the defective column, and the explanation assumes that a switch to the spare column occurs when the column address signals A3C to A0C="0000B" (the appended letter B indicates binary display).
During block write mode, because the two lowest bits A1C and A0C of the column address signals are immaterial, fuses F2a to F3b in a spare column decoder SCD which is a defective address comparator, as shown in FIGS. 3A and 3B, are also provided in series with transistors Ftr2a, Ftr2b, Ftr3a, and Ftr3b to which the remaining upper address signals A3C and A2C are transmitted together with complementary signals /A3C and /A2C of the remaining upper address signals as gate inputs of the transistors Ftr2a to Ftr3b. a fuses which changes to the high voltage potential level only when the defective address is transmitted, the fuses at the high potential is cut. In this conventional example, the fuses F3a and F2a of the column address signals /A3C to /A2C are cut.
First, an operation under the block write mode will be explained when address signals transmitted from an external device designate the defective column in the block write mode.
Prior to providing column address signals, a negative logical OR (a NOR) node /N in the spare column decoder SCD is precharged to the high potential level by a spare column decoder internal node charging signal PRCH. Because the provided column address signals A3C to A2C ="00B", the NOR node /N keeps at the high potential level. Accordingly, a normal column decoder signal CSP changes to the low potential level so that the column selection lines CSL0 and CSL1 (in this case m=0) are not selected. Instead, the NOR node /N and the block write mode signal BW are at the high potential level. Therefore, in spite of potential levels of the column address signals /A1C and A1C, both the spare column selection lines SCSL0 and SCSL1 are selected, and the data on the data line pair 50 not decoded by the DQ buffer 100 is written into the spare columns SCOL0 to SCOL3.
Next, a provided column address contains a defective column, and an example of the operation for the write mode for one bit will be described. Because the provided column address signals A3C to A0C="0000B", the NOR node /N in the spare column decoder SCD keeps at the high potential level. Accordingly, the normal column decoder control signal CSP is at the low potential level, and the column selection lines CSL0 and CSL1 corresponding to the normal column are not selected. Because the block write mode signal BW is at the low potential level, the spare column selection line SCSL0 is selected to be the column selection line CSL in accordance with the column address A1C="0B". Therefore the data in one pair within the data line pairs 50 selected by the column address signal A1C=A0C="0B" is written into the spare column SCOL0. The operation for the address is the same even in the case of a one bit read mode, and is therefore omitted here.
As outlined above, in a conventional semiconductor memory device, for example, even in the case where there is a defective column, there is no problem from the operational point of view in substituting a spare column for the defective column. However, in order to perform the above-described operation correctly, it is necessary to add the same number of spare columns to the normal columns as the number of columns which are a block unit during the block write mode.
In an image memory, it is foreseen that, in future, more and more I/Os will be added (multi-bits) and there will be an increase in the number of columns (which form a block unit) during the block write mode in order to increase a data processing performance of a semiconductor memory device. At the same time, because there will also be an increase in spare columns, the chip area will be increased more than necessary, and, as a result, the problems of decreased yield and an increase in cost will occur.